Process for emulating associative memory

ABSTRACT

A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count. When access to a data page is sought, comparisons are made: 1) between the high order virtual address component of the data page and the high order virtual address component read from the target associative memory entry; and 2) between the multi-digit validity count read from the target associative memory entry and the multi-digit current validity count in the target counter. If there is a full match, the real page address of the requested page is read from the target associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the target associative memory is updated accordingly.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] Reference may be taken to related co-pending U.S. patent application Ser. No. ______ entitled ASSOCIATIVE MEMORY by Bruce A. Noyes and Russell W. Guenthner, filed on even date herewith and assigned to the same Assignee, now U.S. Pat. No. ______.

FIELD OF THE INVENTION

[0002] This invention relates to the art of computer memories and, more particularly, to an emulated associative memory used and maintained as a host computer system emulates a target system running target system software.

BACKGROUND OF THE INVENTION

[0003] A modern computer system with a large memory (called “main memory” herein) may use virtual addressing in which a virtual memory address issued by a processor must be converted to a real (physical) address in the main memory to read or write the addressed storage area. A conversion table, often called a page table, holds the virtual-to-real cross reference information. However, the page table is usually stored in the main memory itself such that accessing the page table to effect a virtual-to-real conversion for each memory access would be very time consuming. Associative memories have been used for many years to speed up this process.

[0004] Associative memories are small, fast memories, directly available to the processor, which store an updateable selection of entries in the page table. The entries are updated when there is a “miss” (the associative memory does not hold the particular virtual-to-real entry requested by the processor) such that the page table must be consulted directly to obtain the requested virtual-to-real address conversion information. However, this particular entry can be sent to the associative memory as a result of the page table access so that the next request for the same virtual-to-real address conversion can be serviced very quickly.

[0005] It is sometimes necessary to clear an entire associative memory by marking all entries “invalid”. Embodiments of the invention serve to perform this function very efficiently.

DESCRIPTION OF THE DRAWING SET

[0006]FIG. 1 is a partially block, partially schematic diagram of a computer system incorporating an embodiment of the invention and illustrating operation when there is an associative memory “hit”;

[0007]FIG. 2 is a view of the computer system of FIG. 1 illustrating a first operation, accessing the page table, when there is an associative memory “miss”;

[0008]FIG. 3 is a view of the computer system of FIG. 1 illustrating a second operation, updating the associative memory, when there is an associative memory “miss”;

[0009]FIG. 4 is a view of the computer system of FIG. 1 illustrating an operation to “invalidate” the entire associative memory simultaneously;

[0010]FIG. 5 is a view of the computer system of FIG. 1 illustrating an operation for directly resetting all validity count fields in the associative memory to a base count and also a related operation to reset the counter to a count offset from the base count;

[0011]FIG. 6 is a view of an associative memory in an embodiment of the invention incorporating a plurality of levels of association;

[0012]FIG. 8 is a view of a host system emulating a target system which includes a target system associative memory; and

[0013]FIG. 8, constituting interconnected FIGS. 8A, 8B, 8C and 8B, is a process flow chart of an embodiment of the invention.

DETAILED DESCRIPTION

[0014] Attention is first directed to FIG. 1 which shows an embodiment of the invention in a computer system which includes a central processing unit (CPU) 1 which includes a processor 3, a storage 4 (local cache and/or other local fast memory) and an associative memory 5. (In some architectures, part or all the storage 4 may be integrated with the processor 3.) The CPU 1 is coupled to an addressable large (“main”) memory 2 having a mass storage device 10. The associative memory 5 has support circuitry including a counter 6, a comparator 7, a switch 8 and a concatenate block 9.

[0015] The associative memory 5 stores a table of entries each of which includes a virtual address field “VirtualTXX”, a corresponding real page address field “RealTXX” and also a multi-digit count in a validity field “VcntXX”.

[0016] In the example chosen to illustrate the embodiment of the invention shown in FIG. 1, a small associative memory 5 is shown, and relatively small address fields are used. It will be fully understood by those skilled in the art that larger associative memories and address fields are commonly used. If a very small 16-bit complete address field is assumed, the example shown uses an offset (lowest order) value, which identifies the position of an addressed block in a page stored in memory, of from 0000 to 1111 as shown at 12 in FIG. 1. The lowest orders of the virtual/real addresses stored in the associative memory 5 are a function of their individual positions in the table and thus also range from 0000 (“00”) to 1111 (“15”). Thus, in the example, the high order virtual and real addresses, stored respectively in the “VirtualTXX” and “RealTXX” fields in the table, each range from 00000000 to 11111111. The validity counter field “VcntXX” can also be any length suitable for a given system, but in the example is assumed to be four bits long such that the range of storage in the validity counter field ranges from 0000 to 1111. Thus, the length of each full entry in the exemplary associative memory is twenty bits. The order of the columns in the table is not critical and the order shown has been chosen only for purposes of illustration.

[0017] During normal operation, the processor 3 may issue a virtual address corresponding to, for example, page 11 in the mass storage device 10 and also an offset value of 1010 identifying the particular block in the mass storage device to be read from or written to. The low order component of the virtual address, say 1001, is used to conventionally address the high order virtual address information stored in the VirtualT09 position, which high order virtual address information is sent to the comparator 7 for comparison with the high order virtual address issued by the processor 3. In addition, the Vcnt09 multi-digit validity value is sent to the comparator 7 for comparison with the current count in the counter 6.

[0018] Assuming that the high order virtual addresses compare and also that the multi-digit validity value matches the current count in the counter 6, the comparator 7 sends an enable (“hit”) signal to switch 8 which responsively effects copy of real address RealT09 to the concatenate block 9 which also receives the offset value, 1010 in the example, from the processor 3. The concatenated full address is sent to the main memory 2 to set up communication between block 1010 of page 1010 and the storage 4 in the CPU 1 to carry out whatever read/write from/to operation is required by the processor 3. (Some systems only require the read/write of full pages from/to main memory 2 and thus need no provision for concatenating an offset value such that the real address output from the switch 8 is the full address sent to the main memory.)

[0019] Referring now to FIG. 2, consider the operation of the system when the processor 3 issues the virtual address for page 13 in the mass storage device 10 and there is a miss in the comparator 7 due to a mismatch between the virtual high order address specified by the processor 3 and the virtual high order address stored in the specified virtual low order address position, say VirtualT04, in the associative memory 5. The comparator 7 sends a miss signal to the processor 3 which knows that it must consult the page table 12 directly in order to obtain the virtual-to-real conversion information for accessing page 13 and thus issues the page table address to obtain this information.

[0020] Similarly, consider the operation when the processor 3 issues the virtual address for page 13 in the mass storage device 10 and there is a miss in the comparator 7 due to a mismatch between the current value stored in the counter 6 and the count stored in the validity count field, say Vcnt04, in the associative memory 5. (This means that the entry is “invalid” even if the high order virtual address is a match; page 13 may not be at the real address specified by RealT04.) The comparator 7 will send the “miss” signal to the processor 3 which will consult the page table 12 directly in order to obtain the current virtual-to-real conversion information for accessing page 13.

[0021] Referring to FIG. 3, following either of these “miss” conditions, the processor has obtained the real address for the page 13 from the page table 12 and sends it to the concatenate block 9 along with the offset, say 0001, in order to establish communications between the storage 4 and block 0001 of page 13 in mass storage device 10 to carry out whatever read/write from/to operation is required by the processor 3.

[0022] In addition, the associative memory 5 is updated with the virtual-to-real translation information for page 13 in the mass storage device 10 so that page 13 can next be accessed much more quickly. The processor sends the high order virtual address information and the real address information for storage as VirtualT04/RealT04 as defined by the low order address information and also enters the current count in counter 6 into the multi-digit validity field Vcnt04 in order to mark this updated entry as “valid”.

[0023] It is sometimes necessary to mark all entries in an associative memory invalid. Attention is now directed to FIG. 4 which shows how this operation is performed very efficiently in the illustrated embodiment of the invention. The processor send an “increment” signal to the counter 6 to advance the count in the counter by one binary digit. (Alternatively, a negative increment or “decrement” may be employed to decrease the count in the counter 6 by one binary digit. Thus, in the claims appended hereto, the term “increment” comprehends both positive and negative increment.) It will be appreciated that this simple step immediately invalidates all entries in the associative memory 5 because succeeding accesses on each low order address will “miss” on the validity count compare until that entry has been updated as shown in FIG. 3 and discussed above.

[0024] However, this procedure must take into account that the counter 6 will eventually “roll over” and again begin to count through the same sequence. Thus, without intervention, it is possible that old entries still resident in the associative memory 5 would inadvertently be marked “valid” when the counter 6 reaches the count(s) stored in one or more of the VcntXX fields. This contingency is treated as shown in FIG. 5.

[0025] A exemplary four-digit length is assumed for counter 6 such that its value range is from 0000 to 1111. When incrementation is used to step the counter 6, it will eventually reach a count of 1111, and a corresponding signal is sent to the processor 3. The processor 3 responds by setting all VcntXX fields in the associative memory 5 to 0000 and setting the count in the counter 6 to 0001. Similarly, when decrementation is used to step the counter 6, it will eventually reach a count of 0001, and a corresponding signal is sent to the processor 3. The processor 3 responds by setting all VcntXX fields in the associative memory 5 to 0000 and setting the count in the counter 6 to 1111. Of course, other base counts and increment values may be employed with suitable adjustment to the details of resetting the counter 6 and the validity count fields of all the entries in the associative memory 5.

[0026] In the embodiment of the invention shown in FIG. 6, a plurality of entries having the same low order address are stored in the associative memory 5 at respective levels of association in ranks 5A, 5B, 5C and 5D, four levels of association having been chosen as the example. Thus, when the processor 3 sends a low order address, say 1010, to the associative memory 5, four virtual high order addresses—VirtualT12A, VirtualT12B, VirtualT12C, VirtualT12D—and four validity count field entries—Vcnt12A, Vcnt12B, Vcnt12C, Vcnt12D—from banks 5A, 5B, 5C, 5D are asserted on respective comparators 7A, 7B, 7C, 7D for comparison against the virtual high order address issued by the processor 3 and the current count in the counter 6.

[0027] Each of the comparators' 7A, 7B, 7C, 7D outputs is coupled as a control signal to a respective switch 8A, 8B, 8C, 8D which, respectively receive the relevant real address entries (“REALA”, “REALB”, “REALC”, “REALD”) stored in the banks 5A, 5B, 5C, 5D. Thus, if there is a full match in any one of the comparators 7A, 7B, 7C, 7D, say comparator 7C, then the output of the comparator 7C is used to enable the switch 8C to send the corresponding real address in bank 5C, i.e., RealT12C, to one of the inputs to an OR-circuit 15. The OR-circuit 15 passes the validated real address to the concatenate block 9 where the offset value provided by the processor is appended to fully develop the address in main memory of the block to be accessed.

[0028] If there is a full miss (in the example, all comparators issue a miss signal “M”), then the page table 12 is consulted to obtain the virtual-to-real address conversion information as discussed above in reference to FIG. 2, and the relevant entry is updated in the associative memory 5 as discussed above in reference to FIG. 3. It is preferable to send the new associative memory entry having a given low order address to the least-recently-used invalid entry in the several banks, 5A, 5B, 5C, 5D in the exemplary embodiment shown in FIG. 6. This is achieved using a conventional LRU block 14 which has access to the associative memory 5 for tracking usage and updates and directs each new update into the appropriate bank 5A, 5B, 5C or 5D which replaces the least-recently-used invalid entry specified by the low order address of the requested page.

[0029] Other embodiments of the invention are implemented in software. For example, as shown in FIG. 7, a target system employing an associative memory 5EM having entries with a multi-digit validity count field is emulated on a host system 20. The host system 20 includes a host processor 21, a host storage 22 and a host memory 23 (typically, a high speed random access memory or “RAM”) into which a software rendition of the target system is loaded. Of interest to the embodiment of the invention shown in FIG. 7, emulated components of the target system further include: emulated storage 4EM, an emulated processor 3EM, an emulated counter 6EM, emulated comparator(s) 7EM, emulated switch(es) 8EM, emulated concatenate block 9EM emulated LRU 14EM and emulated OR circuit 15EM. These emulated components correspond to the similarly numbered hardware components 3, 4, 5, 6, 7, 8, 9 shown in FIG. 1 and, for embodiments employing multiple levels of association, to the components 3, 4, 5A, 5B, 5C, 5D, 6, 7A, 7B, 7C, 7D, 8A, 8B, 8C, 8D, 14 and 15 as shown in FIG. 6. (Those skilled in the art will recognize that some of the emulated components, need not necessarily “exist” in the host memory 23 if the emulation of their function can more easily be carried out during the normal execution of the emulator software. In FIG. 7, all the emulated components are shown within the fast memory 23 for clarity in explaining process/software embodiments of the invention.)

[0030] When the host system 20 is initialized, the host memory 23 is loaded, in the manner well known in the art, with representations of the emulated components of the target system (typically initially stored in main memory 2) including those shown in FIG. 7 which are the target system components used in the practice of process/software embodiments of the invention. Components of the target system may be represented by one to many words in the host memory 23. For example, for the emulated processor 3EM, many words contain representations of each the various elements (registers, counters, etc.) of the processor 3 (FIG. 1). However, manipulation of information among these elements is under control of the host processor 21 during the emulation process in which target system software is being run. Only one word may be needed to store the emulated counter 6EM. The emulated associative memory 5EM may require one or more words of the host memory 23 to store each individual entry. Each emulated component is similarly represented in FIG. 7 in suitable space allocated in the host memory 23, but all manipulation of information among the emulated components is under the control of the host processor 21.

[0031] Thus, those skilled in the art of emulation will understand that it is the host processor 21 which performs the emulation process in communication with the various storage areas in the host memory 23 representing the emulated components of the target system.

[0032] Attention is now directed to the process flow chart of FIG. 8 (interconnected FIGS. 8A, 8B, 8C and 8D) for an alternative explanation of an embodiment of the invention. Thus, FIG. 8 particularly sets forth the emulation process operations pertaining to the emulation of the target associative memory 5EM.

[0033] Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the exemplary embodiments discussed above. Therefore, it is intended to encompass all such variations and modifications as fall within the scope of the appended claims.

[0034] Claim elements and steps herein have been numbered and/or lettered solely as an aid in readability and understanding. As such, the numbering and/or lettering in itself is not intended to and should not be taken to indicate the ordering of elements and/or steps.

[0035] Further, in some or all the claims set forth below, an outline format is employed solely for the purpose of recitation clarity, and the outline level of any particular recited element or step should not be taken as necessarily indicative of the relative stature of that element or step in a given claim. 

What is claimed is:
 1. In a host computer system including a host processor, a host memory and an addressable main memory coupled to the host processor, the main memory storing data pages, at least one data page storing a page table, a process, carried out by the host computer system, for emulating a target computer system running target system software comprising: A) establishing a representation of a target system processor in the host memory; B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count; C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count; D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested: 1) using a low order virtual address component of the requested data page to specify an entry in the target system associative memory; 2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry; and 3) comparing the multi-digit validity count read from the specified target system associative memory entry to the multi-digit current validity count in the target system counter; E) if there are matches: 1) between the requested high order virtual address component and the high order address component read from the target system associative memory; and 2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory; then concatenating the real page address in the specified entry in the target system associative memory with an appended offset value to access a main memory block in the requested data page in main memory;
 2. The process of claim 1 in which, if there is a no-match condition in at least one of steps E)1) and E)2), accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof, thereby obtaining access to the requested data page.
 3. The process of claim 2 in which the entry, in the target system associative memory, specified by the virtual low order address of the requested data page is updated by placing: A) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the specified entry; B) the real page address for the requested data page, as obtained from the page table, into the real page address field of the specified entry; and C) the current count in the target system multi-digit counter into the multi-digit validity count field of the specified entry.
 4. The process of claim 1 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 5. The process of claim 2 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 6. The process of claim 3 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 7. The process of claim 4 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 8. The process of claim 5 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 9. The process of claim 6 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 10. The process of claim 4 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 11. The process of claim 5 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 12. The process of claim 6 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 13. In a host computer system including a host processor, a host memory and an addressable main memory coupled to the host processor, the main memory storing data pages, at least one data page storing a page table, a process, carried out by the host computer system, for emulating a target computer system running target system software comprising: A) establishing a representation of a target system processor in the host memory; B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries in multiple levels of association, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count; C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count; D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested: 1) using a low order virtual address component of the requested data page to specify an entry at each level of association in the target system associative memory; 2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry at each level of association; and 3) comparing the multi-digit validity count read from the specified target system associative memory entry at each level of association to the multi-digit current validity count in the target system counter; E) if there are matches: 1) between the requested high order virtual address component and the high order address component read from the target system associative memory at one level of association; and 2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory at the one level of association; using the real address in the specified entry in the target system associative memory at the one level of association to access the requested data page in main memory.
 14. The process of claim 13 in which, if there is a no-match condition in at least one of steps E)1) and E)2) for all levels of association, accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof, thereby obtaining access to the requested data page.
 15. The process of claim 14 in which the target system associative memory is updated by placing: A) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page; B) the real page address for the requested data page, as obtained from the page table, into the real page address field of the least-recently-used entry; and C) the current count in the target system multi-digit counter into the multi-digit validity count field of the least-recently-used entry.
 16. The process of claim 13 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 17. The process of claim 14 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 18. The process of claim 15 in which all entries in the target system associative memory are selectively simultaneously invalidated by incrementing the target system multi-digit counter.
 19. The process of claim 16 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 20. The process of claim 17 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 21. The process of claim 18 in which the target system multi-digit counter is positively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches all “1”s: A) the target system multi-digit counter is reset to a count of one; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 22. The process of claim 16 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 23. The process of claim 17 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 24. The process of claim 18 in which the target system multi-digit counter is negatively incremented to simultaneously invalidate all entries in the target system associative memory and in which, when the count in the target system multi-digit counter reaches a count of one: A) the target system multi-digit counter is reset to all “1”s; and B) all the multi-digit validity count fields in all entries in the target system associative memory are reset to a count of zero.
 25. In a host computer system including a host processor, a host memory and an addressable main memory coupled to the host processor, the main memory storing data pages, at least one data page storing a page table, a process, carried out by the host computer system, for emulating a target computer system running target system software comprising: A) establishing a representation of a target system processor in the host memory; B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count; C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count; D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested: 1) using a low order virtual address component of the requested data page to specify an entry in the target system associative memory; 2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry; and 3) comparing the multi-digit validity count read from the specified target system associative memory entry to the multi-digit current validity count in the target system counter; E) if there are matches: 1) between the requested high order virtual address component and the high order address component read from the target system associative memory; and 2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory; then concatenating the real page address in the specified entry in the target system associative memory with an appended offset value to access a main memory block in the requested data page in main memory; G) if there is a no-match condition in at least one of steps E)1) and E)2): 1) accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof; and 2) concatenating the real page address obtained from the page table with an appended offset value to access a main memory block in the requested data page in main memory; and 3) updating the entry in the target system associative memory specified by the low order virtual address of the requested data page by placing: a) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the specified entry; b) the real page address for the requested data page, as obtained from the page table, into the real page address field of the specified entry; and c) the current count in the target system multi-digit counter into the multi-digit validity count field of the specified entry; and; H) selectively incrementing the target system multi-digit counter to simultaneously invalidate all entries in the target system associative memory.
 26. In a host computer system including a host processor, a host memory and an addressable main memory coupled to the host processor, the main memory storing data pages, at least one data page storing a page table, a process, carried out by the host computer system, for emulating a target computer system running target system software comprising: A) establishing a representation of a target system processor in the host memory; B) establishing a representation of a target system associative memory in the host memory, the target system associative memory storing a plurality of entries in multiple levels of association, each entry in the target system associative memory being stored in accordance with a low order virtual address component, each entry in the target system associative memory including fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count; C) establishing a representation of a target system multi-digit counter in the host memory, the target system multi-digit counter storing a current validity count; D) when, during the ongoing data processing activity of the target system running target system software, access to a specified data page in main memory is requested: 1) using a low order virtual address component of the requested data page to specify an entry at each level of association in the target system associative memory; 2) comparing a high order virtual address component of the requested data page to the high order virtual address component read from the specified target system associative memory entry at each level of association; and 3) comparing the multi-digit validity count read from the specified target system associative memory entry at each level of association to the multi-digit current validity count in the target system counter; E) if there are matches: 1) between the requested high order virtual address component and the high order address component read from the target system associative memory at one level of association; and 2) between the multi-digit validity count in the target system multi-digit counter and the multi-digit validity count read from the target system associative memory at the one level of association; concatenating the real page address in the specified entry in the target system associative memory at the one level of association with an appended offset value to access a main memory block in the requested data page in main memory; G) if there is a no-match condition in at least one of steps E)1) and E)2): 1) accessing the page table stored in the main memory to obtain the real page address of the requested data page identified by the high order and low order virtual address components thereof; and 2) concatenating the real page address obtained from the page table with an appended offset value to access a main memory block in the requested data page in main memory; and 3) updating the entry in the target system associative memory specified by the low order virtual address of the requested data page by placing: a) the high order virtual address component for the requested data page, as obtained from the page table, into the high order virtual address component field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page; b) the real page address for the requested data page, as obtained from the page table, into the real page address field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page; and c) the current count in the target system multi-digit counter into the multi-digit validity count field of the least-recently-used entry at the level of association defined by the virtual low order address of the requested data page; and H) selectively incrementing the target system multi-digit counter to simultaneously invalidate all entries in the target system associative memory. 